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[VHDL-FPGA-Verilog] CPU

Description: 用Verilog HDL语言写一个简单的处理器CPU。包括IR,Control unit,A,Addsub,G,Counter,8个寄存器。-Verilog HDL language used to write a simple processor CPU. Including IR, Control unit, A, Addsub, G, Counter, 8 registers.
Platform: | Size: 1190912 | Author: sunying | Hits:

[VHDL-FPGA-Verilog] Verilog-HDLTOP-DOWN

Description: 用Verilog HDL的建模来设计一个经简化的只有八条指令、字长为一字节的RISC中央处理单元（CPU）的顶层设计。-Modeling with the Verilog HDL to design a simplified and only eight instructions, word length is a byte RISC central processing unit (CPU) of the top-level design.
Platform: | Size: 43008 | Author: 刘鹏飞 | Hits:

[VHDL-FPGA-Verilog] cpu

Description: 用Verilog语言编写的单周期cpu，实现的指令有 add,addu,addi,addiu,sub,subu,clo,clz,xori,nor,slt,slti,sltu,sltiu,blez,j.-Verilog languages ??with single-cycle cpu, implementation instructions are add, addu, addi, addiu, sub, subu, clo, clz, xori, nor, slt, slti, sltu, sltiu, blez, j.
Platform: | Size: 5120 | Author: yejunjian | Hits:

[VHDL-FPGA-Verilog] cpu

Description: 用verilog描述一个完整的cpu，以完成仿真，仿真结果合理-Complete with a verilog description of the cpu, in order to complete the simulation, the simulation results are reasonable
Platform: | Size: 927744 | Author: 西电 | Hits:

[VHDL-FPGA-Verilog] mdio

Description: cpu与phy通信，让cpu能读写phy芯片，实现通信-cpu communication with phy
Platform: | Size: 2048 | Author: sushaogang | Hits:

[VHDL-FPGA-Verilog] MIPS_cpu_verilog

Description: 带流水线的类MIPS CPU verilog源代码-With lines of class MIPS CPU verilog source code
Platform: | Size: 18432 | Author: 王垚 | Hits:

[VHDL-FPGA-Verilog] 32bit-RISC-CPU-IP

Description: 使用Verilog语言实现的RISC精简指令集CPU IP核，该CPU具有32位数据宽度，5级流水线结构和指令预判和中断处理功能，适合Verilog语言深入学习者参考。-Using the Verilog language implementation of RISC Reduced Instruction Set CPU IP cores, the CPU has a 32-bit data width, 5-stage pipeline structure and instruction pre-judgment and interrupt handling functions for Verilog language learners in depth reference.
Platform: | Size: 33792 | Author: 张秋光 | Hits:

[VHDL-FPGA-Verilog] Digital-Design-Through-Verilog

Description: cpu design an intutive approach raja sekhar 08-12
Platform: | Size: 1724416 | Author: raja | Hits:

[VHDL-FPGA-Verilog] CPU-32

Description: A 32 bit cpu implementation designed on verilog with test bench.
Platform: | Size: 5120 | Author: zi | Hits:

[VHDL-FPGA-Verilog] pipeline_code

Description: 实现了MIPS五级流水CPU,用verilog语言实现-MIPS CPU verilog
Platform: | Size: 15360 | Author: 王博千 | Hits:

[VHDL-FPGA-Verilog] cycle_code

Description: verilog实现了MIPS多周期（5周期）的CPU-verilog MIPS 5 cylce
Platform: | Size: 15360 | Author: 王博千 | Hits:

[VHDL-FPGA-Verilog] pc-matrix

Description: 简单CPU verilog代码，完全按照COA中描述的结构，是微程序实现-simple structure cpu code, using verilog-HDL, totally struct the organization according to the COA,
Platform: | Size: 11264 | Author: sonicgk | Hits:

[Software Engineering] mips--cpu

Description: 本文基于32位 MIPS CPU的体系架构，采用Xilinx ISE 9.1i软件，通过使用Verilog语言编写了32位MIPS单周期和多周期CPU的程序，完成了其逻辑设计并进行了仿真测试。-Based on a 32 MIPS CPU architectures using the Xilinx ISE 9.1i software, write a 32-MIPS, single cycle and multi-cycle CPU program completed its logic design and simulation tests using the Verilog language.
Platform: | Size: 314368 | Author: 朱祖建 | Hits:

[VHDL-FPGA-Verilog] RISC-CPU

Description: 用FPGA实现一个简易的CPU，采用精简指令集结构，每一条指令有16bit，高三位为指令操作数，后13位为地址，该CPU能实现8种指令操作，分别有HLT（空一个中期）ADD（相加操作）SKZ（为零跳过）AND（相与操作）XOR（异或操作）LDA（读数据）STO（写数据）JMP（无条件跳转指令）。cpu包括8个部件，分别为时钟发生器、指令寄存器、累加器、算术逻辑单元、数据控制器、状态控制器、程序计数器、地址多路器，各个部件之间的相互操作关系由状态控制器来控制，程序指令存放在初始rom中，本例程存放在存储器初始文件中。 PS：为什么没有Verilog选项呢-A simple CPU, FPGA implementation to streamline the instruction set architecture, each instruction 16bit, high three operands for the instruction, the 13 address, the CPU can achieve the eight kinds of instruction operations, respectively, HLT (a medium-term empty) ADD (add operation) SKZ (zero skip) AND (phase operation) the XOR (exclusive OR operation) LDA (read data) STO (write data) JMP (unconditional jump instruction). cpu consists of eight parts, clock generator, the instruction register, accumulator, arithmetic logic unit, the data controller, the state controller, the program counter, the address multiplexer, the various components interoperate relations by the state controller to control, program instructions stored in the initial rom the routines stored in memory the initial file. PS: Why is there no Verilog options.
Platform: | Size: 3147776 | Author: vice | Hits:

[VHDL-FPGA-Verilog] risc_cpu-OK

Description: 夏宇闻 verilog数字系统设计教程源码 第二版，实现了简单的RISC CPU。印刷版有误，已改正。- A simple RISC CPU Verilog HDL source code. Work well.
Platform: | Size: 9216 | Author: Jian SUN | Hits:

[Other] single-clock-CPU

Description: 单时钟周期CPU，verilog语言编写，quartusII运行-A single clock cycle CPU
Platform: | Size: 2104320 | Author: 周骁 | Hits:

[VHDL-FPGA-Verilog] pipelined_computer

Description: 基于de2-board的汇编以及verilog的五段流水线CPU代码，适合新手学习-Based on the de2-board assembler, and the five-stage pipelined CPU verilog code, suitable for novice learning
Platform: | Size: 8127488 | Author: laoxu | Hits:

[VHDL-FPGA-Verilog] code

Description: cpu的主要功能部件verilog简单代码-main features of cpu verilog simple code
Platform: | Size: 8192 | Author: ws | Hits:

[ARM-PowerPC-ColdFire-MIPS] ARM-Verilog-HDL-IP-CORE

Description: ARM处理器的IP核，用verilog编写的，对处理器和相关的CPU架构知识有很大帮助。-ARM processor IP core, written in verilog processor and CPU architecture knowledge.
Platform: | Size: 74752 | Author: shen jun | Hits:

[VHDL-FPGA-Verilog] cpu

Description: 用verilog语言写的简单cpu，在处理器功能和结构上，对于初学者有很大帮助。-Verilog language write simple cpu, processor function and structure of great help for beginners.
Platform: | Size: 15360 | Author: shen jun | Hits:
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